FIG. 1 is a simplified block diagram of a conventional 4-way set-associative cache memory apparatus. The reference numeral 1 designates address data used for the cache memory apparatus. Address data 1 is composed of address tag 11, entry address 12 and word address 13. Using entry address 12, the cache memory apparatus accesses four-way tag memories 2 and data memories 3. Each "way", is understood to comprise a group of address tags and data sets. A 4-way set-associative cache memory apparatus comprises four ways; four sets of data for one entry, accordingly, can be stored in the cache memory.
Tag memories 2 are provided with corresponding comparators 4, and data memories 3 with corresponding word selectors 5. Each data memory 3 stores information consisting of a plurality of words; each word is provided with a corresponding address.
Word selectors 5 are provided with a way selector 6 which outputs the contents of a selected way to a data processor (not shown in FIG. 1). The content of the way is selected in response to signals supplied by comparators 4 in accordance with the result of a comparison.
In general, an N-way cache memory system utilizes an n-way set-associative method of data mapping. This method divides a memory into N-banks having a plural number of entries. Art entry of the respective banks is determined by the decoded results of plural bits at the middle of an address. The method further compares a tag address stored in the same entry of respective banks with the tag address supplied by a CPU to determine whether there is a "hit" or a "miss". N-way cache memories are known in the prior art. See, for example, "Practical Use of Cache Memory", Computer Design, September, 1988, pp. 116-118.
Operation of the conventional cache memory apparatus is as follows. Still referring to FIG. 1, upon receipt of address data 1 from a data processor in a reading cycle, tag memories 2 and data memories 3 are accessed on the basis of entry address 12. Tag memory 2 of each corresponding way delivers the content of an accessed address to the corresponding comparator 4. Data memory 3 of each corresponding way delivers the content of the accessed address to the corresponding word selector 5. Each word selector 5 in turn selects the content of the word corresponding to word address 13 of address data 1 before delivering the selected data to way selector 6.
Each comparator 4 compares address tag 11 of address data 1 to those address tags delivered from each tag memory 2. If the compared results between these address tags coincide with each other, that is, there is a "cache-hit", comparator 4, via a hit judging unit 13d, outputs a coincidence signal to the way selector 6. On receipt of a coincidence signal, way selector 6 outputs the content of the corresponding word to the data processor.
Conversely, if the compared result between these address tags do not coincide, in other words, during a "cache-miss", the cache memory apparatus accesses the main memory to read certain data from an address of the main memory corresponding to address data 1, and then delivers the read-out data to the data processor. Using a conventional least-recently used (LRU) algorithm, the cache memory apparatus clears the cache memory regions storing the least-usable data to allow storage of the above readout data of the main memory in the cleared memory region.
FIG. 2 is a simplified block diagram of a conventional data processor system (8) with cache memory 83 incorporating separate data-storing and instruction-storing cache memory apparatus. Reference numeral 81 designates a data processor connected to main memory 84 and an optional direct memory access unit 94 through a bus line 82. Instruction-storing cache memory 83a and data-storing cache memory 83b are connected to the middle of bus line 82. Data processor 81 is connected to a chip selecting circuit 86 through access-property signal line 85. Chip selecting circuit 86 in turn is connected to cache memories 83a, 83b through chip-selecting signal lines 87a, 87b.
Operation of the conventional data processor system (8) is as follows. During a data writing cycle in accordance with an access property supplied by data processor 81, chip selecting circuit 86 generates a chip-selecting signal, either the instruction-storing cache memory 83a or data-storing cache memory 83b is selected. Data processor 81 accesses either cache memory 83a or cache memory 83b selected by the chip-selecting signal and selects an instruction or data to be fetched.
As a result, if data should be cached in accordance with an attribute related to instructions or data, a number of cache memory apparatus corresponding to the number of attributes must be provided. This results in a large data processing system. Furthermore, the volume of data stored according to each attribute is variable. This causes data to be stored unevenly resulting in poor utilization of the cache memory apparatus itself.
An object of the invention accordingly is to provide a cache memory apparatus having memory regions corresponding to attributes of information, capable of accessing the required memory regions using information attributes.
Another object is to provide a novel, set-associative cache memory apparatus which arranges information requiring storage in each way of a memory region composed of n-ways in accordance with an attribute of the information so that the needed way can be accessed by the cache memory apparatus using an attribute.
Another object is to provide a novel multiple data processor system which sets memory regions accessible by each of a plurality of data processors, inside a cache memory apparatus, so that the needed memory region can be accessed by information specifying any of the data processors.
Another aspect of the invention is as follows. Referring again to FIG. 2, and assuming that the cache memories 83a, 83b comprise a 4-way set-associative system, the cache memory sets the access type of data stored in every two-ways. "Access type" means a selected one of the following kinds of data, INSTRUCTION, DATA, or co-processor command. When the data processor 81 operates in a reading or writing mode, a signal related to the access type of data of a corresponding address is generated. The cache memory 83 will refer to the access type of data from the data processor (81). During a reading operation of the data processor 81, if a cache-miss occurs, the cache memory stores data in accordance with the access type of data from the data processor (81). On the other hand, when the bus transfer is to an apparatus other than data processor 81, e.g., DMA apparatus 94 on the same bus as the main memory, the cache memory 83 monitors the address in order to maintain coincidence of data with the main memory 84, at which time the cache memory 83, when a cache-miss occurs, carries out no processing. When a cache-hit occurs during the writing operation to the main memory 84, the corresponding data in the cache memory is rewritten. In this case, when an apparatus other than data processor 81 is a bus master, the apparatus may not issue the information related to the access type of data. The cache memory 83 accordingly, rewrites the corresponding data without referring to the access type of data.
Referring now to FIG. 15, which is a flow chart explaining one aspect of data processor in the conventional cache memory apparatus, the access types stored in the ways A and B among four-ways A through D are preset as "INSTRUCTION"; those stored in the ways C and D are preset as "DATA". In the main memory 84, the memory space of task 0 is assumed to be positions 0000 through 2FFF, the access type of positions 0000 through 1FFF is assumed to be "INSTRUCTION", and the access type of positions 2000 through 2FFF is assumed to be "DATA". The data stored at positions 1000 through 1FFF is called data group 0. On the other hand, task 1 is assumed to have a memory space the same as task 0 and the access type of positions 0000 through 0FFF is assumed to be "INSTRUCTION". That of positions 1000 through 2FFF is "DATA". Data stored at positions 1000 through 1FFF is called data group 1. In addition, cache memory 83 is adapted to enable the access type of data stored in every 2-ways to be set.
In FIGS. 2 and 15, initially, the task 0 is assumed to be running. When the data processor 81 reads data in the data group 0 and the cache memory 83 prompt a cache-miss, the cache memory stores 4-word data including the corresponding data in accordance with the access type. In this case, since the access type of data group 0 is "INSTRUCTION", data is stored in the way A or B using path (1). Next, when task 0 is completed and task 1 starts to run, the DMA apparatus 94 changes the task, at which time the DMA apparatus becomes the bus master. The cache memory 83 thereby monitors the address.
The cache memory 83, while address monitoring, rewrites data regardless of the access type, i.e., on the basis of the result of comparing addresses, only when a cache-hit occurs. The data of data group 1 is written in the way storing the data of data group 0 of task 0, in other words, in the way A or B where the access type is "INSTRUCTION", despite the fact that the access type is "DATA", as depicted by path (3) in FIG. 15. Thereafter, when the data processor 81 operates in the reading mode and the cache memory 83 prompts a cache-miss, the aforesaid data is stored in the way C or D where the access type is "DATA", as shown by path (4).
As a result, data of different access types, but having the same address, simultaneously exist in the cache memory 83. Thereafter, when the access type setting of cache memory 83 is changed to, for example, a "don't care" ("INSTRUCTION" and "DATA" are mixed), as shown by path (5) and the data processor 81 performs a reading operation with respect to data of the data groups 1 and 2, since the access types of data stored in the ways A through D are all the same, all the data are hit so that data in the cache memory 83 collides, shown as path (6). Furthermore, when a multicache system is adopted, collision of data occurs on the data bus.
As depicted in FIG. 15, the conventional cache memory has the problem that, when the data of main memory 84 is largely rewritten and the data having the same address, but different access types, simultaneously exist, and the access type of cache memory is changed and read, collision of data occurs.
A further object of the invention accordingly is to provide a cache memory apparatus wherein a plurality of stored data are not simultaneously output.
A still further object is to provide a cache memory apparatus and method avoiding collision of data when a plurality of data having the same address but different access type are to be simultaneously read.